1. Field of the Invention
The present invention relates to a method and an apparatus for detecting a defect on a wafer.
2. Description of the Related Art
In general, fine patterns of semiconductor integrated circuits formed on a wafer are inspected for detecting pattern defects after performing a semiconductor fabrication process step or a series of semiconductor fabrication process steps. As semiconductor devices become more highly integrated and a diameter of the wafer becomes larger, the inspection process for detecting defects on the wafer is more frequently carried out. Therefore, overall manufacturing time for manufacturing the semiconductor device has been significantly increased, thereby raising the manufacturing cost of the semiconductor devices.
Conventionally, an individual gray level corresponding to each of pixels on the wafer is measured, and the gray level of a target pixel and the gray levels of neighboring pixels adjacent to the target pixel are compared with each other. Then, the gray level difference is calculated. The inspection process detects defects of the wafer by using the gray level difference. The inspection process is classified into an array mode and a random mode. While the array mode compares respective cells in a chip on the wafer for detecting defects, the random mode compares respective die for detecting defects. The array mode is usually used in semiconductor memory device fabrication process, and the random mode is usually used in logic device fabrication process. Hereinafter, the inspection process for detecting defects will be explained for the array mode.
In general, the widespread array mode inspection process uses a threshold value for detecting defects on the wafer. The gray level difference between the target pixel and the neighboring pixels adjacent to the target pixel is compared with a preset threshold value. When the gray level difference is greater than the preset threshold value, the target pixel is indicated as a defective pixel. On the contrary, when the gray level difference is less than the threshold value, the target pixel is indicated as a non-defective pixel.
FIG. 1 is a schematic diagram showing a conventional inspector. Referring to FIG. 1, a wafer 12 on which predetermined process steps have been carried out is loaded on a support 14 for detecting process defects on the wafer. The wafer 12 is loaded/unloaded to/from the support 14 by the conventional loading mechanism such as a robot arm. A light source 10 irradiates a light to each cell on a surface of the wafer 12. Then, the light is reflected from the surface of the wafer 12. The reflected light is detected by an image detecting means 16 including a photo-sensor, and as a result, an analog image signal is generated. The analog image signal is converted into a digital image signal by an analog-to-digital converter (ADC). Thus, gray levels corresponding to respective pixels comprising each cell on the wafer are formed. The gray level is processed with 8-bit digital signal, so that each pixel of the cell may have 256 kinds of gray levels. Therefore, gray levels corresponding to every pixel form the digital image corresponding to a cell on the wafer, and all the digital images corresponding to every cell forms an image map corresponding to one sheet of the wafer. Then, a data process unit 20 generates a raw datum. The raw datum is a gray level difference between the gray level of the target pixel and the gray level of the neighboring pixel adjacent to the target pixel. On the other hand, a threshold presetting unit 24 presets a threshold value, which is used for judging whether a defect is formed on the wafer. The raw datum is calculated into an absolute value, and is compared with the threshold value. The defect on the wafer is detected using a detecting unit 22. The detecting unit 22 includes a central process unit (CPU) and a co-processor, and detects the defect on the wafer by using a main program and a sub-program. The result of the detecting unit 22 is displayed on a monitor of the operating terminal 26.
FIG. 2 is a diagram explaining the generation of the raw datum by the data process unit shown in FIG. 1.
Referring to FIG. 2, a light is irradiated on a first cell A that is an arbitrary cell on the wafer at an arbitrary time t0. A first image I1 corresponding to the first cell A is obtained. Next, a light is irradiated on a second cell B adjacent to the first cell at a time t0+1 after a lapse of unit time from the time t0, and a second image I2 corresponding to the second cell B is obtained. A third image corresponding to the third cell, a fourth image corresponding to the fourth cell, and a fifth image corresponding to the fifth cell are sequentially obtained in the same manner. Thus, the image map corresponding to an entire surface of the wafer is obtained. The size of the cell is determined such that the same pattern is repeated for every image obtaining step. Each of the images is represented as the gray level of the pixels comprising the respective cells on the wafer, and the gray level is binary digital data. Therefore, an image difference I1-I2 between the first and second images is the binary digital datum.
FIG. 3 is a diagram explaining a process for detecting the defects on the wafer by using the detecting unit shown in FIG. 1. FIG. 3 shows arbitrary 3 cells neighboring each other on the wafer for simplicity. The same alphabetic letter indicates a pixel located on the same position on different cells, and the same numeric letter indicates an identical cell.
An experiment shows that the gray levels of each pixel B1, B2, and B3 of FIG. 3 are 50, 100, 50, respectively, and the gray levels of each pixel C1, C2, and C3 of FIG. 3 are 60, 30, 60, respectively. That is, the B2 pixel is more luminescent than the B1 and B3 pixels, and the C2 pixel is less luminescent than the C1 and C3 pixels. The raw datum of the B2 pixel is the gray level difference between the B2 pixel and the adjacent pixels B1 and B3. That is, the raw datum of the B2 pixel is calculated as the gray level difference of (gray level of B2 pixel−gray level of B1 pixel) and (gray level of B2 pixel−gray level of B3 pixel). In the same way, the raw datum of the C2 pixel is calculated as the gray level difference of (gray level of C2−gray level of C1) and (gray level of C2−gray level of C3). According to the present experiment, the raw datum of the B2 pixel is 50, and the raw datum of the C2 pixel is −30. The negative raw datum is converted into the same positive value by converting into an absolute value. When the threshold value is 40, the B2 pixel is checked as a defective pixel and the C2 pixel is checked as a non-defective pixel.
FIG. 4 is a flow chart illustrating a conventional method of detecting a defect on the wafer.
Referring to FIG. 4, a light is irradiated on a surface of the wafer on which a thin film is deposited, and in step S10, gray levels of each pixel on the wafer are formed. In next step S20, the raw datum that is the gray level difference between the target pixel and the neighboring pixel is generated, and in step S30, the threshold value that is a criterion for judging defectiveness after compared with the raw datum is preset. In step S40, the raw datum is checked whether or not the value is negative. When the raw datum has a negative value, the raw datum is converted into the positive value by using the absolute value of the negative raw datum in step S42. In subsequent step S50, the raw datum is compared with the threshold value, and when the raw datum is more than the threshold value, the target pixel is checked as a defective pixel in step S60.
However, the conventional detecting method has the following problems:
First, a killer defect, meaning a serious defect, and a non-killer defect, meaning a non-serious defect, are simultaneously detected because all of the target pixels of which the absolute value of the raw datum is more than the threshold are checked as a defective pixel. Therefore, the killer defect and the non-killer defect are not easily separated from each other.
A process of after-develop inspection (ADI) is carried out on a surface of the wafer on which 0.09 mm design rule is applied for detecting a micro-bridge that is a killer defect found on a gate of a non-versatile memory (hereinafter, referred to as NVM). According to the ADI data measured by the STEALTH (trade name, a detecting apparatus made by KLA-Tencor Co. Ltd. U.S.A.), about 50% of the detected defects were sub-defect that is a common defect found under the layer, and about 40% of the detected defects were a non-visual defect such as the false defect that is not visible through the scanning-electron microscope (SEM) and caused by the interference of the incident light or the operating error of detecting apparatus. That is, about 90% of the detected defects were non-killer defects.
FIG. 5 is a diagram showing the gray level difference with respect to the defect type detected on the NVM. The horizontal axis of the diagram indicates the defect type, and the vertical axis of the diagram indicates the gray level difference.
FIG. 5 confirms that the gray level differences of the sub-defect and the false defect are greater than the gray level difference of the bridge defect that is the killer defect generated during the NVM fabricating process. Therefore, when the threshold value is exemplarily preset as about 30 for detecting the bridge defect, the sub-defect and the false defect are also detected with the bridge defect. Therefore, the bridge defect is not separated from the sub-defect and the false defect.
Second, when the negative raw datum is converted into a positive value by using an absolute value of the negative raw datum, an originally positive raw datum is not distinguished from the converted positive raw datum. Therefore, the defect corresponding to the originally positive raw datum and the defect corresponding to the converted positive raw datum are simultaneously detected, so that the detected defect cannot be verified.
An inspection process is carried out on a surface of the wafer on which 0.123 mm design rule is applied after patterning process for forming a S-poly (storage node with polysilicon), and the respective gray levels of the detected defects are measured. The inspection discloses not only, for example, a striation defect which is a common defect of the S-poly patterning process, and the false defect, but also a leaning defect that is a killer defect of the S-poly patterning process. The false defect is not visible through the scanning-electron microscope (SEM), and it is caused by the interference of the incident light or the operating error of detecting apparatus.
FIG. 6 is a diagram showing the gray level difference with respect to the defect type during the S-poly patterning process. The horizontal axis of the diagram indicates an arbitrary position on the surface of the wafer, and the vertical axis of the diagram indicates the gray level difference.
Referring to FIG. 6, when the gray level difference is in a range between about 20 and about 60, not only the leaning defect but also the striation defect is most frequently detected. Therefore, when the threshold value is preset as one of the range between about 20 and about 60, the leaning defect and the striation defect are always detected together.
The false defect is more frequently detected because the design rule is becoming smaller and smaller. Therefore, inspection time for detecting the killer defect is getting longer, thereby reducing the productivity of fabricating semiconductor devices.